(1) Field of the Invention
The present invention relates to a method for making a semiconductor substrate having a Silicon-Germanium (Si—Ge) layer for improved semiconductor device performance. More particularly the method utilizes a high-temperature process step to deposit a seed layer to minimize the discontinuities in the seed layer. The Si—Ge layer grown on the seed layer results in improved electrical continuity. The Si—Ge layer can be grown at a lower temperature to minimize the change in the dopant profile while retaining the improved electrical continuity. This two-temperature process is particularly useful for forming Si—Ge bases on heterojunction bipolar transistors (HBT) with minimal change in dopant profile when the Si—Ge bases must extend over an oxide isolation when providing the base contact for the Si—Ge base.
(2) Description of the Prior Art
In the past few years the Si—Ge heterojunction bipolar transistor has received much attention because of improved device performance over the conventional NPN transistor. As the size of the bipolar transistor is reduced, the high frequency performance (maximum cut-off frequency) is limited by the ability to further reduce the base width and to improve the emitter injection efficiency. Also, as the base dopant is further increased in concentration, the parasitic capacitance and the like limit the upper frequency range. One method of overcoming this high frequency limitation is to make an HBT having a Si—Ge base to modify the bandwidths in the base to improve the emitter injection efficiency and to improve electron mobility.
Several methods of fabricating heterojunction bipolar transistors have been reported in the literature. For example, U.S. Pat. No. 6,346,453 B1 to Kovacic et al. describes a method for making an HBT using a sacrificial layer over a Si—Ge layer to protect an area for where an emitter is later formed. U.S. Pat. No. 5,523,243 to Mohammad describes a method for making a triple HBT by forming a Si/Si—Ge superlattice for the base and a second superlattice for the emitter. A rectangular groove is etched through the emitter to make the extrinsic base contact. U.S. Pat. No. 5,256,550 to Laderman et al. describes a method for forming a strained SixGe1-x layer for the base of a bipolar transistor to improve the emitter injection efficiency. Huang in U.S. Pat. No. 6,251,738 B1 describes a method for making a Si—Ge base on a mesa and then removing the Si—Ge adjacent to the mesa. In a second embodiment a mesa is formed surrounded by a trench that is filled with a dielectric layer, and a selective epitaxial Si—Ge is grown on the mesa top surface to form the Si—Ge base.
One of the problems associated with making an HBT is not being able to form a good quality boron-doped Si—Ge layer for the intrinsic base, while providing a continuous Si—Ge layer over a non-crystalline surface, such as SiO2 for making electrical contact to the extrinsic base area.
To better understand this problem, FIGS. 1 and 2 depict the sequence of steps for growing a Si—Ge layer by the current typical process. FIG. 1 shows a schematic cross-sectional view of a partially completed NPN hetero-junction bipolar transistor (HBT) on a silicon substrate 10. The Fig. shows an N− subcollector 14 formed in the substrate 10. Shallow trench isolation (STI) regions 12 are formed in the substrate over the subcollector 14. The STI regions surround the device areas 2. An insulating layer 16 and a polysilicon layer 18 are deposited, and openings 4 are formed in layers 16 and 18 over the device areas 2 and extend over the STI regions 12. To make this HBT, a relatively thin seed layer 20 is grown on the device areas 2 and is also formed over the STI regions 12 and over the polysilicon layer 18. The seed layer 20 over the non-crystalline STI 12 has relatively large grain sizes that result in discontinuities (voids), as indicated by G in FIG. 1. As shown in FIG. 2, for a boron-doped base in an HBT, an in-situ boron-doped Si—Ge layer 22 is epitaxially grown on the seed layer 20 over the device areas 2, and because of the large grain size (discontinuities) in the seed layer over the STI 12, the Si—Ge also has discontinuities. This results in poor electrical conductivity and uniformity between the intrinsic base 2 and the base contact, which is formed in the region C over the patterned polysilicon layer 18 outside the STI region. To avoid excessive out-diffusion of boron from the Si—Ge base, the seed layer 20 and the Si—Ge layer 22 are deposited at relatively low temperatures that results in the large grain sizes with longer reaction time and poor electrical properties.
There is still a need in the semiconductor industry to improve upon the current process for making a doped single-crystal Si—Ge intrinsic base with minimal out-diffusion, while providing good electrical contact between the intrinsic base and the extrinsic base contact region.